If the gate voltage is large relative to V GS, I D is set mainly by Rs and is not greatly influenced by V GS variations. Basic JFET ‘offset-biasing’ system.Ī more accurate way of biasing the JFET is via the ‘offset’ system of Figure 4(a), in which divider R1-R2 applies a fixed positive bias to the gate via Rg, and the source voltage equals this voltage minus V GS. In practice, the V GS value needed to set a given I D varies widely between individual JFETS, and the only sure way of getting a precise I D value in this system is to make Rs a variable resistor the system is, however, accurate enough for many applications, and is the most widely used of the three biasing methods.įIGURE 4.

Suppose that an I D of 1mA is wanted, and that a V GS bias of -2V2 is needed to set this condition the correct bias can obviously be obtained by giving Rs a value of 2k2 if I D tends to fall for some reason, V GS naturally falls as well, and thus makes I D increase and counter the original change the bias is thus self-regulating via negative feedback. The simplest of these is the ‘self-biasing’ system shown in Figure 3, in which the gate is grounded via Rg, and any current flowing in Rs drives the source positive relative to the gate, thus generating reverse bias.įIGURE 3. Three basic JFET biasing techniques are in common use. The JFET can be used as a linear amplifier by reverse-biasing its gate relative to its source terminal, thus driving it into the linear region. All practical circuits shown here are specifically designed around the 2N3819, but will operate equally well when using the MPF102.

This month’s article looks at basic usage information and applications of JFETs. Two of the oldest and best known n-channel JFETs are the 2N3819 and the MPF102, which are usually housed in TO92 plastic packages with the connections shown in Figure 1 Figure 2 lists the basic characteristics of these two devices. Most JFETs are n-channel (rather than p-channel) devices. Basic characteristics of the 2N3819 and MPF102 n-channel JFETs.

I GSS max (= gate leakage current at 25° C) I DSS (= drain-to-source current with V GS = 0V) Outline and connections of the 2N3819 and MPF102 JFETs. JFETs are low-power devices with a very high input resistance and invariably operate in the depletion mode, i.e., they pass maximum current when the gate bias is zero, and the current is reduced (‘depleted’) by reverse-biasing the gate terminal.įIGURE 1. Last month’s opening episode explained (among other things) the basic operating principles of JFETs. » Skip to the Extras Practical JFET circuits.

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